1. Field of the Invention
The present invention relates generally to a dual-port memory, and more specifically, to a dual-port memory used in data transmission between multiprocessor systems.
2. Description of the Background Art
FIG. 3 is a block diagram showing one working embodiment of a dual-port memory. In FIG. 3, a dual-port memory 1 includes two input/output ports. One input/output port (hereinafter referred to as A port) is connected to a host system 3 through a system bus 2. The other port (hereinafter referred to as B port) of dual-port memory 1 is connected to a slave system 5 through a system bus 4. Host system 3 and slave system 5 may be of any type for processing data. For example, a multiprocessor system including a central processing unit (CPU) is often used. Therefore, host system 3 includes a host CPU 31, a read only memory (ROM) 32 and a random access memory (RAM) 33, and slave system 5 includes a slave CPU 51, a ROM 52 and a RAM 53. Dual-port memory 1 includes memory means therein. The memory means is accessible individually by host system 3 and slave system 5.
Dual-port memory 1 as described above is often used for exchanging data between host system 3 and slave system 5. For example, if host system 3 and slave system 5 operate asynchronously to each other, it is difficult to make direct data transmission between the systems. Performing the data transmission through dual-port memory 1 allows data to be transferred between the systems when necessary. Thus, the throughputs of the systems are improved, and systems 3 and 5 operate in a cooperative manner each other, so that a larger system can be structured.
FIG. 4 is a block diagram showing one embodiment of a structure of a conventional dual-port memory. In FIG. 4, placed in a memory cell array 10, as shown in FIG. 5, are a plurality of word lines and bit lines crossing each other, and a memory cell is placed at a crossing point of each word line and each bit line. A decoder 11a and a sense amplifier 12a for A port, and a decoder 11b and a sense amplifier 12b for B port are provided for memory cell array 10. A port address data from host system 3 is applied to decoder 11a through an address input terminal 13a, and B port address data from slave system 5 is applied to decoder 11b through an address input terminal 13b. Provided in parallel between sense amplifier 12a and an A port data input/output terminal 14a are a tri-state buffer 15a for writing data, and a tri-state buffer 16a for reading data. A write enable signal is applied from host system 3 to a control terminal of tri-state buffer 15a through an A port write signal input terminal 17a. The output state of tri-state buffer 15a is controlled based on the write enable signal. A read enable signal is applied from host system 3 to a control terminal of tri-state buffer 16a through an A port read signal input terminal 18a. Tri-state buffer 16a has its output state controlled based on the read enable signal. Similarly, for the B port, a tri-state buffer 15b for writing data, and a tri-state buffer 16b for reading data are provided in parallel between a sense amplifier 12b and a B port data input/output terminal 14b. A write enable signal is applied from slave system 5 to a control terminal of tri-state buffer 15b through a B port write signal input terminal 17b. Tri-state buffer 15b has its output state controlled based on the write enable signal. A read enable signal is applied from slave system 5 to a control terminal of tri-state buffer 16b through a B port read signal input terminal 18b. Tri-state buffer 16b has its output state controlled based on the read enable signal.
FIG. 5 is a diagram showing an input/output structure for one memory cell in memory cell array 10 shown in FIG. 4. A plurality of memory cells 101 are disposed in a matrix of rows and columns. In memory cell array 10, as shown in FIG. 5, two word lines 103a and 103b are disposed for each row for memory cell 101, and two bit lines 104a and 104b are disposed for each column. One memory cell 101 is provided with two transfer gate transistors 102a and 102b. Word line 103a, bit line 104a, and transfer gate transistor 102a are provided for the A port. Word line 103b, bit line 104b, and transfer gate transistor 102b are provided for the B port. In the dual-port memory shown in FIGS. 4 and 5, the A port and B ports are thus each provided with an entirely separate and independent access system. Memory cell array 10 is therefore simultaneously accessible from host system 3 and slave system 5.
In a thus structured dual-port memory 1, tri-state buffer 15a is activated in response to a write request from host system 3, and write data from host system 3 is applied to sense amplifier 12a. Tri-state buffer 15b is activated in response to a write request from slave system 5, and write data is applied to sense amplifier 12b. Furthermore, tri-state buffer 16a is activated in response to a read request from host system 3, and data read out from an activated and selected memory cell is output to the host system through A port data input/output terminal 14a. Tri-state buffer 16b is activated in response to a read request from slave system 5, and data read out from an activated and selected memory cell is output to slave system 5 through B port data input/output terminal 14b.
It could be considered that a whole multiprocessor system is structured in a following manner. First, there exists a single and complete processor, and then a slave system utilizing a part of data from a host system is added to the single and complete processor which is used as the host system, whereby a whole multiprocessor system can be realized. In this case, as shown in FIG. 6, if a dual-port memory address region could be superimposed on the address space 34 of the memories in the host system controlled by host CPU 31, a slave system could be added without providing any program change in the host system, because the address space of the memories controlled in the host system would not be expanded.
Conventionally, however, it has been impossible to provide the address region of the dual-port memory in the address space of the memories inside the host system. When host CPU 31 tries to read out data from the dual-port memory, data collisions take place, because internal memory regions having the same addresses are also designated.
Therefore, if a slave system is added to an already completed host system, as shown in FIG. 7, it is necessary to keep the address region of the dual-port memory from overlapping the address space of the internal memory of the host system, and, therefore, cumbersome reprogramming is required of the host system.
Now, the above-described problem will be described more in detail by referring to the engine control of an automobile.
In case of the engine control of an automatic shift car, data for an engine control system is necessary for controlling its transmission devices. However, as is the case with a manual shift car such as a sports car, the control of transmission devices is not performed by a microcomputer in some cases. In other words, among automobiles installed with the same engines, some require transmission control by a microcomputer, and others do not. When a microcomputer system for engine control is designed taking into account whether a microcomputer for transmission control is necessary or not, different programmings are necessary depending upon the existence or absence of data transmission processings between the host system and dual-port memory, which is troublesome and often responsible for problems.